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FPGA Development
FPGA Development
Our expertise ranges from design of companion FPGA with a few hundred gates to SoC designs with multi-million gates FPGA.

ProcSys FPGA development team is capable of delivering fully validated ready to deploy FPGA solutions based on a set of requirements from the customer. Our expertise ranges from design of companion FPGAs with a few hundred gates to SoC (System on Chip) designs with multi-million gates FPGAs.

Solutions
 

Intellectual Property (IP) development: Custom design solutions

System-on-Chip designs and implementation of standards

Proof-of-concept: ASIC verification in FPGA

Conversion of ASIC to FPGA

Performance accelerators

Companion FPGAs for ASSP components

Processor interface designs: Bus translators and converters

Control and monitoring sub-systems

Expertise
 

Architecture design

HDL coding

Test bench with test scripts

Functional verification

Timing Verification

Device fitting: Pin out and place & route

Validation on hardware platform

ProcSys Advantage
 

Alliance with major PLD vendors: Xilinx and Altera

Experience in low, medium and high complexity designs

Expertise in hardware & software work partitioning for optimum performance

  and cost.

Expertise in building test benches and test automation scripts for FPGA

  verification

In house board and software development teams for building validation boards

  and test software

Well established and proven design methodologies & review processes

Domain expertise in datacom, telecom, aerospace/industrial and consumer

  electronics

Long term support contract for product maintenance and enhancements

Capability Matrix
Features Expertise
  FPGA Families  

Xilinx: Virtex II, Virtex E, Virtex, Spartan 3, Spartan 2, Spartan XL and CPLDs
Altera: Stratix II, Startix, Apex II, Flex 10K and EPLDs

  Operating Frequency

 

200 MHz (external) and 250 MHz (internal)
  Package size

 

1152-pin BGA (maximum)
  I/O Technology

 

LVTTL, HSTL, SSTL, PCI, DDR SDRAM etc.
  Language

 

VHDL & Verilog
  Environment

 

Altera Quartus & Max Plus II, Xilinx ISE
  Verification Environment

 

Mentor Graphics ModelSIM
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